Primary Skills
 

• Performed timing analysis, validation, and debugging across various PVT (Process, Voltage, Temperature) corners using Tempus.
   
• Hands-on experience with Tempus DMMMC flow for Static Timing Analysis (STA).
   
• Involved in STA setup, convergence, reviews, and sign-off for both scan and functional modes.
   
• Analyzed timing reports and reviewed unconstrained endpoints to ensure comprehensive coverage.
   
• Strong expertise in STA methodologies with a solid understanding of noise, crosstalk, and On-Chip Variation (OCV) effects.
   
• Experienced in timing closure at both block and full-chip levels for advanced process nodes such as 22nm, 16nm, and 5nm.
   
• Collaborated closely with design, synthesis, and PNR teams to provide feedback and drive smooth timing closure.
   
• Proficient in scripting with Tcl and Python for STA automation and analysis.
   
• Familiar Cadence-based STA flows.
   
• Prior experience working on power-domain-based designs is an added advantage.