Required Skills:

Over 5 years of experience in modeling at various levels of abstraction using System Verilog RNM and custom UDNs.

Proficient in verification of complex mixed-signal products at block, subsystem, and chip-top levels.

Strong grasp of analog design concepts and mixed-signal system architectures.

Hands-on exposure to Power Management, PLL/Synthesizers, ADC, DAC, Bandgap References, Oscillators, Phase Interpolators, SerDes, and digital control systems.

Skilled in developing and debugging UVM verification environments and testbenches.

Proficient with Cadence Xcelium/DMSO, Synopsys VCS, Virtuoso, and SimVision.

Experience with co-simulation of analog models and digital RTL/Gate + SDF.

Proficient in using Cadence vManager for tracking verification metrics and managing regressions.

Expertise in writing self-checking testcases, and implementing functional/code coverage and formal verification.

Understanding of AMS/RF architectures and schematic-level debug.

Effective collaboration with cross-functional teams including system architects, analog/digital designers, and digital verification teams.

Strong analytical skills with the ability to quickly learn and apply new technologies